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Re: [cdt-dev] Memory view and monitor

> On 29 Jan 2020, at 19:28, <Anton.Krug@xxxxxxxxxxxxx> <Anton.Krug@xxxxxxxxxxxxx> wrote:
> It doesn't work on other peripherals, because that CoreTimer is the only peripheral I modeled for our RISC-V target.
> Under 'breaking it' I mean the peripheral is designed to be accessed in 32-bit mode and so does the simulated model of the peripheral, however in the simulated model I broke the spec and allowed it to be accessed in 8-bit chunks as well, then the peripheral view works as shown in the screenshot. 

If the SVD defines the registers as 32-bit, and you see 8-bit accesses, then you probably hit a bug in the GME peripheral registers viewer, I don't think it has to do with CDT.



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