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Re: [cdt-dev] Memory view and monitor
  • From: <Anton.Krug@xxxxxxxxxxxxx>
  • Date: Wed, 29 Jan 2020 17:28:38 +0000
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  • Thread-topic: [cdt-dev] Memory view and monitor

The question was just to rule out if we are talking about 2 different things. 
And I was in the mindset it's inheriting the access functionality from the memory view.

Not just Cortex-M, RISC-V can have memory-mapped peripherals as well. The screenshot looks at what I expect to happen (because I enabled 8-bit accesses).
It doesn't work on other peripherals, because that CoreTimer is the only peripheral I modeled for our RISC-V target.
Under 'breaking it' I mean the peripheral is designed to be accessed in 32-bit mode and so does the simulated model of the peripheral, however in the simulated model I broke the spec and allowed it to be accessed in 8-bit chunks as well, then the peripheral view works as shown in the screenshot. 

From: Liviu Ionescu <ilg@xxxxxxxxxx>
Sent: 29 January 2020 16:46
To: Anton Krug - M31845 <Anton.Krug@xxxxxxxxxxxxx>
Cc: cdt-dev@xxxxxxxxxxx <cdt-dev@xxxxxxxxxxx>
Subject: Re: [cdt-dev] Memory view and monitor
EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe

> On 29 Jan 2020, at 17:59, <Anton.Krug@xxxxxxxxxxxxx> <Anton.Krug@xxxxxxxxxxxxx> wrote:
> I followed your document:
> And in Peripherals I can select the peripheral I made quickly and then it gets opened as Memory View's monitor, see attachment. Do I do something wrong?

I'm afraid I do not understand the question.

Yes, on Cortex-M devices, the peripherals are memory mapped, and the peripheral registers view is just a more advanced memory view.

What do you expect to happen?

Does it work with other peripherals?

> Btw when I target the simulation platform and 'break' it on purpose to support byte accesses then the monitor gets populated nicely with the values.

... not following you... :-(



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