Skip to main content
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [List Home]
[threadx-dev] Proposal: hardware CI for ThreadX on RISC-V

Hi all,

Our RISC-V ports and regression tests currently run only on QEMU. At the moment, no CI job executes them on real RISC-V hardware.

Over the past couple of weeks, Frederic and I have been discussing on adding real hardware testing for Eclipse ThreadX. We would like to propose using Cloud-V's LAVA (Linaro Automated Validation Architecture) service for this purpose.

Cloud-V is a community platform developed and managed by 10xEngineers. It uses LAVA to run boot-level tests on RISC-V boards. The same infrastructure is used by KernelCI to test U-Boot, OpenSBI, and Linux. The service is free to use.

We propose the following workflow for Eclipse ThreadX:

  1. GitHub Actions builds the RISC-V test ELF files.
  2. The workflow submits a LAVA job to the Cloud-V lab.
  3. The lab boots each test on a RISC-V board and captures the serial output.
  4. The test results are returned to the GitHub Actions workflow as JUnit reports and used to determine the PR status.

The proposed change set contains only CI configuration and test scaffolding. No ThreadX kernel source code is modified. As an initial milestone, we plan to enable this workflow for the BananaPi BPI-F3 ThreadX port.

Please feel free to share any questions or suggestions. If you're interested in contributing or helping with this effort, we'd be happy to hear from you.

I will present the proposal in more detail during the next weekly committers meeting. Please join if you would like to discuss it. The presentation slides are attached.


Best,
Akif

Engineer @ 10xEngineers
Co-developed Cloud-V
CM @ Eclipse ThreadX
akifejaz.dev

Back to the top