Hi Eugene, thanks for the reply.
There was two other issues, I'll restate them here:
This CSR,
{ "boom_dbg", 0x7c1 }
Is not a general CSR from the RISC-V specs, it seems to be a
custom CSR for the The Berkeley Out-of-Order RISC-V Processor.
It clashes with one of our own custom CSRs.
This CSR,
{ "scontext",
0x7aa },
is wrong. It should be 0x5A8 according to the latest priv spec
(and also latest debug spec).
Best regards,
Yes, the list appears outdated.
I'll remove the old entries.
Thanks,
Eugene
Hello,
I found some issues in disassembler-riscv.c,
in static const CSRDefinition csr_regs[] :
These CSRs,
{ "ustatus", 0x000 },
{ "uie", 0x004 },
{ "utvec", 0x005 },
{ "uscratch", 0x040 },
{ "uepc", 0x041 },
{ "ucause", 0x042 },
{ "utval", 0x043 },
{ "uip", 0x044 },
{ "sedeleg", 0x102 },
{ "sideleg", 0x103 },
are not in the latest spec, RISC-V Privileged Architectures
Version 20241017 ratified.
I found them in the 20190608 version of the priv spec, but
they have since been removed.
Can they be removed here, or are they needed for backwards
compatibility to old specs?
This CSR,
{ "boom_dbg", 0x7c1 }
Is not a general CSR from the RISC-V specs, it seems to be a
custom CSR for the The Berkeley Out-of-Order RISC-V Processor.
It clashes with one of our own custom CSRs.
This CSR,
{ "scontext",
0x7aa },
is wrong. It should be 0x5A8 according to the latest priv spec
(and also latest debug spec).
Best regards,
Anton Bäckström
Software engineer
Frontgrade Gaisler
Frontgrade Gaisler AB, Kungsgatan 12, SE-411 19, GÖTEBORG, Sweden.
+46 (0) 31 775 8650, www.gaisler.com
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