FullCommand:
	{FullCommand}
	(
	(label = [Label] ':')?
	(
			 (  (rep=RepN)?   lcp=LeftCommandPart 'with'   rcp=RightCommandPart )
			|(  (rep=RepN)? ->lcp=LeftCommandPart )
			|(( (rep=RepN)?   'nul'?   		    'with')? rcp=RightCommandPart )
		) 
		| (startrep = Repeat) 
		| (endrep   = EndRepeat ) 
		| (spec     = SpecialCommands)
	)
	';' lf=Linefeed
; 

RepN:
	{RepN}
	'rep' ((times = INT)|(const = ConstNameResolver ))
; 

//  *** *** *** FETCH VALUE 

FetchArgument:
	fa = (NonVectorRegister|AnyId|IntegerLookingNumericValue|AnyArrayElement)
; 

FetchOperation:
	lp = '[' 
	v = FetchArgument ( gbo = GetBiasOperation val = FetchArgument )?
	rp = ']'
; 

UnaryBiasInsideFetchOperation:
	lp = '[' 
	((val = NonVectorRegister uo = UnaryOperation)|(uo = UnaryOperation val = NonVectorRegister))
	rp = ']'
;

AnyValueFetchOperation:
	avfo = (FetchOperation|UnaryBiasInsideFetchOperation)
;

// *** *** *** *** *** *** *** *** *** ***
// *** LEFT COMMAND PART ***
// *** *** *** *** *** *** *** *** *** ***

LeftCommandPart:
	{LeftCommandPart}
	lcmd = ( MemoryReadCommand|MemoryWriteCommand|StackCommand|RegiserDirectModifying|ConditionalJump
			 |ConditionalSkip|ConditionalReturn|PswrModifying|FtwOrWtwOrBoth 
	) 
; //|RegisterVariableCopying|VariableRegisterCopying

MemoryReadCommand:
	(  rvreg += Register (',' rvreg += Register)? ) ( Equal avfo = AnyValueFetchOperation (',' ftwwtw = FtwOrWtwOrBoth)? )?
;
//Conflicts with RegiserDirectModifying ?eq=

MemoryWriteCommand:
	(lvfo = AnyValueFetchOperation) (Equal rvreg += Register (',' rvreg += Register)? (',' ftwwtw = FtwOrWtwOrBoth)? )?
; //eq=

RegiserDirectModifying:
	( rregs += NonVectorRegister (',' rregs += NonVectorRegister)? ) 
	Equal 
	(
		( lregs += NonVectorRegister (',' lregs += NonVectorRegister)? ) |
		( var = AnyId)|(arrelem = IntegerArrayElement)
	)
	('set'|'addr')?
; //eq=

// *** *** *** *** *** *** *** *** ***
// *** RIGHT COMMAND PARTS ***
// *** *** *** *** *** *** *** *** ***

RightCommandPart:
	rcmd = (EmptyCommand
			|ArithmeticCommandShortage|ArithmeticCommand|UnaryModificatedRegister|LogicalCommand
		    |ShiftOperation|ShiftOperationShortage
		    |MaskOperation|VsumOperation
		    |ResolverSingleActivatableVectorRegister|ResolverSingleLogicalNonVectorRegister|BinaryCommandWithNoOutput
		    |StoreVregs //|VectorLogicalCommand
	)
; 

// *** *** *** *** *** *** *** *** *** ***
// *** *** SCALAR REGISTER COMMANDS *** ***
// *** *** *** *** *** *** *** *** *** ***


ArithmeticCommandShortage:
	(lreg=NonVectorRegister) (sae=ShortageArithmeticEquals)
		rr1 = (NonVectorRegister|AnyId|AnyArrayElement|AnyNumericConstValue) 
		( 
			bo = BinaryArithmeticOperation 
		  	rr2 = (NonVectorRegister|AnyId|AnyArrayElement|AnyNumericConstValue) 
		)?
	(carryop=PlusOrMinus 'carry')? 'noflags'?
	//( ( shiftop=PlusOrMinus shift = (IntValue|HexValue))? carryop=PlusOrMinus 'carry')? 		'noflags'?
; //shift must be '-1' or '1' //(NonVectorRegister|IntValue|HexValue) rreg = (NonVectorRegister|AnyId|AnyArrayElement|AnyNumericConstValue) 
// TODO 30-10-14 diff. If conflicted try => 

ArithmeticCommand:
	(lreg = NonVectorRegister eq=Equal)?
			rr1 = (NonVectorRegister|AnyId|AnyArrayElement|AnyNumericConstValue) 
			bo = BinaryArithmeticOperation 
			rr2 = (NonVectorRegister|AnyId|AnyArrayElement|AnyNumericConstValue) 
	( 
		( shiftop=PlusOrMinus shift = (IntValue|HexValue) )? 
		carryop=PlusOrMinus 'carry'
	)? 
	'noflags'?
; // shift = (IntValue|HexValue)