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Re: Printing logic diagram sample in 3.1 [message #187111 is a reply to message #187055] |
Fri, 08 July 2005 15:35 |
Eclipse User |
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Originally posted by: none.us.ibm.com
Welcome to gdi+ and advanced graphics.
Feel free to submit a bug report. What DPI is your display set at?
"Rainer Spritzendorfer" <rsprit@cnc-cybernetic.com> wrote in message
news:daleb1$td7$1@news.eclipse.org...
> When printing the four-bit adder sample with v3.1, the connections are
> printed at a bigger scale than all the other parts (see attached image).
> Is this a regression in 3.1 or am I doing something wrong?
>
> Regards
>
> Rainer Spritzendorfer
>
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Re: Printing logic diagram sample in 3.1 [message #187141 is a reply to message #187118] |
Fri, 08 July 2005 15:44 |
Eclipse User |
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Originally posted by: none.us.ibm.com
Of course, to avoid this problem in your own application, turn off
antialiasing when printing.
"Rainer Spritzendorfer" <rsprit@cnc-cybernetic.com> wrote in message
news:dam6nm$ve0$1@news.eclipse.org...
> Randy Hudson wrote:
>> Welcome to gdi+ and advanced graphics.
>>
>> Feel free to submit a bug report. What DPI is your display set at?
>>
>
> 96dpi, OS is Windows 2003 Server
>
>> "Rainer Spritzendorfer" <rsprit@cnc-cybernetic.com> wrote in message
>> news:daleb1$td7$1@news.eclipse.org...
>>
>>>When printing the four-bit adder sample with v3.1, the connections are
>>>printed at a bigger scale than all the other parts (see attached image).
>>>Is this a regression in 3.1 or am I doing something wrong?
>>>
>>>Regards
>>>
>>>Rainer Spritzendorfer
>>>
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