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[Code Gen] State machine guards [message #1855613] Sun, 23 October 2022 10:26 Go to next message
Eclipse UserFriend
Hello.
In the SimpleSM example of Papyrus project there is a note on the state diagram that time event parameters are defined using the MARTE VSL specification. I wonder if there are similar "standard" ways of specifying other special cases on the diagram:

1. Does Papyrus Software Designer support the [else] guard in state machines? What is the recommended way of specifying it on the diagram to work with software generation?

2. The UML specification (v2.5.1, p. 315) states: A guard constraint may involve tests of orthogonal States of the current StateMachine, or explicitly designated States of some reachable object (for example, "in State1" or "not in State2"). Does Papyrus Software Designer support this too? What's the recommended way to include it in the diagram to make it working with code generation?

I'm normally interested in C/C++ code generation, but I think the above questions are not language specific.

Best regards,
Tomasz
Re: [Code Gen] State machine guards [message #1855666 is a reply to message #1855613] Wed, 26 October 2022 03:14 Go to previous messageGo to next message
Eclipse UserFriend
Dear Tomasz,

the code generator supports an [else] guard in the context of a choice state. An outgoing transition of a choice state without guard is implicitly an [else] guard.

In general, the complete PSSM (precise semantics of SMs) specification is supported. The generator assumes that a guard is an opaque expression that contains an arbitrary Boolean C++ expression. In order to write expressions based on the current state, a developer needs to know that the generator stores the current state in the attribute activeStateID which is typed with the generated enumeration StateIDEnum.
Re: [Code Gen] State machine guards [message #1855741 is a reply to message #1855666] Sun, 30 October 2022 16:55 Go to previous message
Eclipse UserFriend
Thank you for your reply, Ansgar. Now it's clear to me.
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