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| Re: Vhdl code generation from UML model using acceleo [message #1766860 is a reply to message #1766858] |
Wed, 28 June 2017 06:36  |
Eclipse User |
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Hi
There are a variety of examples of generating code/text from UML. However generating VHDL is much harder unless your model is trivial. 'Real' computers have substantial language support for pointers and allocation/garbage collection of dynamic memory and underlying memory management units. VHDL is typically targetted at a much more simplistic execution engine where you may avoid dynamic memory altogether or must refactor pointer into indexes and allocation into fixed size arrays. I doubt that you will find examples that do this. I recommend that you use one or more M2Ms to go from a UML model to a VHDL model, you should find that the VHDL model to text (if you need it) is available for free with a VHDL support tool.
Regards
Ed Willink
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