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Home » Modeling » Papyrus » [UML ports modeling - Papyrus](How to design a system architecture on Papyrus with port communication between classes ?)
[UML ports modeling - Papyrus] [message #1702548] Thu, 23 July 2015 07:21 Go to next message
Stephane N. is currently offline Stephane N.Friend
Messages: 2
Registered: July 2015
Junior Member
I wish to make the diagram on attached file in Papyrus

This is a system organized as follows :

• Each " Class_x " is described by a state machine .
• Class_A drives Class_B with information coming from Class_C . The information conveyed by the ports.
• The I_1 and I_2 interfaces contain operations (data flow : methods with parameters ) .
o I_2 contains the operation [ calcul_A (int a) ] : Class_C broadcasts on port " port_C " the signal calcul_A (a ) through I_2 ;
o I_1 contains the operation [ calcul_B (int b1, b2 char ) ] : Class_A broadcasts on port " port_A " the signal calcul_B ( b1, b2 ) through I_1 .
o ports are used to convey calcul_A( int) and calcul_B (int, char) data stream.

My difficulties are the following :
1. What types are the ports? For example port_A has a provided interface and a required interface.
2. How does the data transmission occur through the ports ?

Thank you in advance for your reply and I remain available for additional information.
Re: [UML ports modeling - Papyrus] [message #1703126 is a reply to message #1702548] Tue, 28 July 2015 17:52 Go to previous messageGo to next message
Christian Damus is currently offline Christian DamusFriend
Messages: 1206
Registered: July 2009
Location: Canada
Senior Member

Hi,

1. The interfaces must be of types that use and/or realize interfaces
as appropriate. For example, Port port_A would commonly have as its
type some Class that has a Usage dependency on I_2 and an
InterfaceRealization to I_1 (possibly inherited from some general
class). Whether such class is created as a "one-off" for this purpose
or whether it has intrinsic usefulness in other contexts as well is
down to you.

2. Some Class, Component, Collaboration, or other kind of
StructuredClassifier would contain parts of Class_A, Class_B, and
Class_C types. These parts would be wired together by their ports via
assembly Connectors owned by the containing composite. These
connectors may be typed by Associations, or not. Ultimately, how this
is all manifest in code is entirely down to you: what the meaning of a
part, a port, a connector, or an interface is is quite flexible.

HTH,

Christian


On 2015-07-23 13:35:18 +0000, Stephane Nouketchessi said:

> I wish to make the diagram on attached file in Papyrus
>
> This is a system organized as follows :
>
> • Each " Class_x " is described by a state machine .
> • Class_A drives Class_B with information coming from Class_C . The
> information conveyed by the ports.
> • The I_1 and I_2 interfaces contain operations (data flow : methods
> with parameters ) .
> o I_2 contains the operation [ calcul_A (int a) ] : Class_C
> broadcasts on port " port_C " the signal calcul_A (a ) through I_2 ;
> o I_1 contains the operation [ calcul_B (int b1, b2 char ) ] :
> Class_A broadcasts on port " port_A " the signal calcul_B ( b1, b2 )
> through I_1 .
> o ports are used to convey calcul_A( int) and calcul_B (int,
> char) data stream.
>
> My difficulties are the following :
> 1. What types are the ports? For example port_A has a provided
> interface and a required interface.
> 2. How does the data transmission occur through the ports ?
>
> Thank you in advance for your reply and I remain available for
> additional information.
>
> <image>
Re: [UML ports modeling - Papyrus] [message #1703728 is a reply to message #1703126] Tue, 04 August 2015 12:23 Go to previous message
Stephane N. is currently offline Stephane N.Friend
Messages: 2
Registered: July 2015
Junior Member
Thanks for your explanations,
I will try to use it to continue my system design
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