Import:
   'Import' importedNamespace = QualifiedNameWithWildcard
;
  
QualifiedNameWithWildcard:
   QualifiedName '.*'?
;

//File Fpga.mod
MemArea Fpga
{

Import FrequencyGenrator.*
//File FrequencyGenerator.mod <--- Defines the Module FrequencyGenerator as a 30 Byte Structure
Import ADConverter.*
//File ADConverter.mod  <--- Defines the Module ADC Converter as a 16 Byte Structure

	Version 12
	Description "Configuration Memory Layout for the fpga"

	Module FrequencyGenerator channel1
	Module FrequencyGenerator channel2
        Module ADConverter input
} 

for (module : pck.elements.filter(Module))
{
    generateModule(moduleIt)
}