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Can Xtext support System Verilog [message #1413418]

Thu, 28 August 2014 13:17

Eleanor Richie

Messages: 125
Registered: August 2014

Senior Member

Hello everyone,
I am an newbie to Xtext and would like to use it for writing System Verilog. Can Xtext grammar support System Verilog? if Yes, What can be the limitations for writing system verilog? If No, can you please explain why it can't.

Thanks,

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Re: Can Xtext support System Verilog [message #1432053 is a reply to message #1413418]

Fri, 26 September 2014 14:36

Jens Kuenzer

Messages: 29
Registered: October 2009

Junior Member

If you think about copy an past the grammar from IEEE spec and are ready to go. Then no it is not that simple. For example I think the `include in system verilog is something that is difficult to implement in xtext. If you ask me if it is possible then yes, xtext seems for me very flexible and customizable. But if you are going to implement a given language then you might really need to do a lot of this customization.

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Re: Can Xtext support System Verilog [message #1433789 is a reply to message #1413418]

Mon, 29 September 2014 08:40

Sebastian Zarnekow

Messages: 3118
Registered: July 2009

Senior Member

Hi Shereen,

there are professional tools for Verilog that are built with Xtext so I
think it is feasible but not something that I would consider
straight-forward.

Regards,
Sebastian
--
Looking for professional support for Xtext, Xtend or Eclipse Modeling?
Go visit: http://xtext.itemis.com

Am 28.08.14 15:43, schrieb Shereen Hussein:
> Hello everyone,
> I am an newbie to Xtext and would like to use it for writing System
> Verilog. Can Xtext grammar support System Verilog? if Yes, What can be
> the limitations for writing system verilog? If No, can you please
> explain why it can't.
>
> Thanks,
>

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