Skip to main content


Eclipse Community Forums
Forum Search:

Search      Help    Register    Login    Home
Home » Language IDEs » C / C++ IDE (CDT) » Assembly code error with Cygwin toolchain(Error - unknown register "r0", "r1", r2")
Assembly code error with Cygwin toolchain [message #1720970] Fri, 22 January 2016 09:20 Go to next message
chetana wasnik is currently offline chetana wasnikFriend
Messages: 3
Registered: January 2016
Junior Member
I am using Cygwin toolchain. I am facing a problem with my assembly language code, it says unknown register "r0".........."r5". I am working on NS9215 microcontroller., please suggest if I am using the right toolchain or not?
Re: Assembly code error with Cygwin toolchain [message #1721020 is a reply to message #1720970] Fri, 22 January 2016 15:59 Go to previous messageGo to next message
Tauno Voipio is currently offline Tauno VoipioFriend
Messages: 742
Registered: August 2014
Senior Member
Cygwin is a toolchain to run UNIX-like programs on Windows operating system, using Intel processors.

Your processor is an ARM926EJ-S, which needs a cross-compilation toolchain.


--

Tauno Voipio
Re: Assembly code error with Cygwin toolchain [message #1721136 is a reply to message #1721020] Mon, 25 January 2016 06:48 Go to previous messageGo to next message
chetana wasnik is currently offline chetana wasnikFriend
Messages: 3
Registered: January 2016
Junior Member
Thanks for your reply.
But when using a Cross GCC toolchain, still I am facing the same problem.
Re: Assembly code error with Cygwin toolchain [message #1721144 is a reply to message #1721136] Mon, 25 January 2016 08:09 Go to previous messageGo to next message
Jonah Graham is currently offline Jonah GrahamFriend
Messages: 416
Registered: June 2014
Senior Member
Hi,

Which toolchain (i.e. program downloaded from internet) are you using?

If you are targetting an ARM device, and you have no ARM toolchain already, I recommend launchpad.net/gcc-arm-embedded

Jonah
Re: Assembly code error with Cygwin toolchain [message #1721147 is a reply to message #1721136] Mon, 25 January 2016 08:29 Go to previous messageGo to next message
Tauno Voipio is currently offline Tauno VoipioFriend
Messages: 742
Registered: August 2014
Senior Member
Please post the details:
- which host operating system (Windows?)
- which cross-toolchain?
- the piece of the assembly code not accepted.
- which version of Eclipse and CDT?


--

Tauno Voipio
Re: Assembly code error with Cygwin toolchain [message #1721160 is a reply to message #1721147] Mon, 25 January 2016 10:43 Go to previous messageGo to next message
chetana wasnik is currently offline chetana wasnikFriend
Messages: 3
Registered: January 2016
Junior Member
Windows, Cross ARM GCC, Eclipse IDE for C/C++ Developers - Version: Luna Service Release 2 (4.4.2)

#define INTR_DISABLE(stat) \
asm volatile ( \
"mrs %0,cpsr;" \
"mrs r4,cpsr;" \
"orr r4,r4,#0xC0;" \
"msr cpsr,r4" \
: "=r"(stat) \
: \
: "r4" \
);
Re: Assembly code error with Cygwin toolchain [message #1721172 is a reply to message #1721160] Mon, 25 January 2016 13:07 Go to previous message
Tauno Voipio is currently offline Tauno VoipioFriend
Messages: 742
Registered: August 2014
Senior Member
This compiles, and has been in use for as long as there has been Atmel ARMs:

/* Interrupt disable (kernel internal - for speed) */

#define PS_I (1 << 7) /* interrupt disable */
#define PS_F (1 << 6) /* fast interrupt disable */

static NOINLINE NAKED void disable_int(void)
{
uint32_t tmp;

__asm__ volatile (
"adr %[t],1f\n\t" /* -> 32 bit code */
"bx %[t]\n\t" /* enter 32 bit mode */

".align 2\n\t"
".code 32\n"

"1:\n\t"
"mrs %[t],cpsr\n\t" /* get current PSR */
"orr %[t],%[t],%[ps_i]\n\t" /* insert interrupt disable bit */
"msr cpsr,%[t]\n\t" /* update current PSR */
"bx lr\n\t" /* return in 16 bit mode */

: [t] "=l" (tmp)
: [ps_i] "i" (PS_I)
);
}


The code is for Thumb mode, drop the adr, .code32 and first bx lines for ARM. You can change the ps_i argument to PS_I|PS_F for full disable.

I doubt that the assembler complains about the low registers in your above code, but please take the semicolons out and terminate the statements with a '\n'.

If you create a separate function like mine, you can let the compiler to select the most suitable temporary register instead of casting r4 in concrete. The ARM code generator prefers to use the registers r0 to r3 for temporary use if they are not occupied as function arguments. The compiler is smart enough to inline the function when it is advantageous, and some level of optimization is selected (I prefer -Os).






--

Tauno Voipio
Previous Topic:Where to See Active Build Configuration?
Next Topic:Could not be resolved
Goto Forum:
  


Current Time: Fri Mar 29 02:20:58 GMT 2024

Powered by FUDForum. Page generated in 0.02792 seconds
.:: Contact :: Home ::.

Powered by: FUDforum 3.0.2.
Copyright ©2001-2010 FUDforum Bulletin Board Software

Back to the top